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Enrique
ealeman.kikito@gmail.com
203-927-0070
4642 Owens Drive apt 202
Pleasanton, CA 94588
Embedded Firmware Engineer
14 years experience W2
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Summary

Experienced VLSI ASIC engineer with full breadth of understanding in Logic Design, Functional verification, System Test, SoC bring up and FPGA emulation. Has in depth knowledge of programming Languages and operating systems (Linux/AIX). Currently developing embedded software on IBM PPC for a custom SoC. Actively looking for opportunities in embedded software in a cutting edge project.

Experience
Embedded Firmware Engineer
Information Technology
Jan 2013 - present
  • Developing software on PPC 476 embedded processor for a networking and Fiber channel SoC for delivery to cross functional RTOS firmware team. (SoC to be used in IBM Mainframe Server).
  • Responsible for development of firmware low level boot-code initialization sequence, recovery functions and common libraries for mainline operations using assembly/C code.
  • Actively engaged in bringing up firmware in an FPGA based Emulation Environment and debugging low-level firmware and hardware using debug tools such as in-circuit debuggers (JTAG, RISCwatch), hardware and protocol analyzers.
Firmware Fiber channel Embedded Software C Assembler RTOS Fiber Optics
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Verification Engineer
Information Technology
Jan 2011 - Jan 2013
  • Defined the scope of unit verification for a PCIe switch ASIC and developed the test plan for the same ASIC. (ASIC for IBM Mainframe Server).
  • Developed test bench and generators for unit simulation of the PCIe switch ASIC and integrated BFMs to the verification environment.
  • Developed tests in Fusion (IBM’s equivalent of OVM/UVM) to verify the link functionality of the root complex for both Gen2 and Gen3 PCIe complex.
  • Developed the coverage plan for the PCIe switch ASIC and worked with cross functional teams to achieve coverage to enable tape-out.
  • Created and maintained the register modeling to verify the register functionality of the PCIe sub system.
  • Became very familiar with the PCIe architecture and worked closely with the cross functional hardware design/bring up teams.
  • Advocated and architected a generic unit simulator for IBM PCIe building block designs to minimize resource utilization, maximize reuse between programs and drive best practices.
C++ Simulation Database Design
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ASIC Hardware Design Engineer
Information Technology
Jan 2009 - Jan 2010
  • Micro architected and developed logic to provide maintenance and recovery function for an Ethernet Adapter ASIC. Designed the I2C to the DCR bridge. Micro architected and designed reset sequencing logic to handle custom system specific boot strap.
  • Micro architected recovery matrix and sequencing for system failure tolerance to avoid host downtime.
  • Performed full development cycle from Architecture, design and test of a hardware FPGA flow control driver to interface with a high speed Ethernet network adapter.
Database Design
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System Test Engineer
Information Technology
Jan 2007 - Jan 2008
  • Delivered in system bring up and validation of an IO network and Fiber channel adapter ASIC. Responsibilities included initial card power-on, system recognition of the adapter, ASIC initialization and mainline functionality testing.
  • Developed and executed the hardware test plan for Fiber channel IO adapter. Utilized various debug tools including PPC RiscWatch, oscilloscope and PCIe logic analyzer. Delivered the test plan in a highly aggressive schedule to support the system delivery.
Debug Code UAT Fiber channel Fiber Optics
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Edit Skills
Non-cloudteam Skill
Education
Bachelor's in Computer Engineering
University of Connecticut, 1999 - 2003
Skills
Fiber Optics
2021
7
Database Design
2013
3
RTOS
2021
3
C
2021
2
Debug Code
2008
2
Fiber channel
2021
2
UAT
2008
2
Assembler
2021
1
C++
2013
1
Embedded Software
2021
1
Firmware
2021
1
Simulation
2013
1
Linux
0
1
Languages
Spanish, Fluent/Bilingual